Thermal Noise Measurements in a Reverberation Chamber

Two models describing properties of the thermal noise power emerging from an antenna mounted in a reverberation chamber are described. The first compares the reverberation chamber to an over-moded cavity acting as a black-body source; the second describes the noise in terms of the antenna noise temperature. Measurements based on the antenna noise temperature model show the noise power to be dependent on the position of the rotating mechanical stirrer. The correlation of the antenna noise temperature with the stirrer position dependent antenna mis-match factor is shown. When a signal is injected into the chamber measurements of the signal to noise power ratio show that this ratio is dependent on the stirrer position and also the position of the signal source within the chamber. These results have significant consequences for the detection of weak signals from radiating sources in a reverberation chamber

An Experimental Study of the Signal to Noise Ratio of Radiated Emissions in the Presence of Thermal Noise in a Reverberation Chamber

In this paper the phenomenon of thermal noise present in a reverberation chamber and received through an antenna within the chamber is reviewed. The consequences of the thermal noise are described in terms of the observed signal to noise ratio of a signal radiated by an equipment-under-test placed at a number of positions in the chamber. It is shown that the observed signal-to-noise ratio is dependent on both the position of the equipment-under-test within the chamber and on the stirrer position

High-Sigma Performance Analysis using Multi-Objective Evolutionary Algorithms

Semiconductor devices have rapidly improved in performance and function density over the past 25 years enabled by the continuous shrinking of technology feature sizes. Fabricating transistors that small, even with advanced processes, results in structural irregularities at the atomic scale, which affect device characteristics in a random manner. To simulate performance of circuits comprising a large number of devices using statistical models and ensuring low failure rates, performance outliers are required to be investigated. Standard Monte Carlo analysis will quickly become intractable because of the large number of circuit simulations required. Cases where the number of samples exceeds are known as “high-sigma problems”. This work proposes a highsigma sampling methodology based on multi-objective optimisation using evolutionary algorithms. A D-type Flip Flop is presented as a case study and it is shown that higher sigma outliers can be reached using a similar number of SPICE evaluations as Monte Carlo analysis

Implementation of Reduced Precision Integer Epigenetic Networks in Hardware

This paper details the development of a resource efficient implementation of the Artificial Epigenetic Network (AEN) concept, based on reduced precision integer mathematics, and the translation of this implementation into hardware via a Field Programmable Gate Array (FPGA) to provide improvements in resource utilisation and execution speed while not sacrificing the unique benefits provided by the epigenetic mechanism. Validation of the implementation’s performance on the inverted pendulum task is obtained and compared to that of previous AENs, as well as experiments to determine how far the precision of the network may be reduced while still maintaining an acceptable degree of performance

Multi-objective digital circuit block optimisation based on cell mapping in an industrial electronic design automation flow

Abstract Modern electronic design automation (EDA) tools can handle the complexity of state‐of‐the‐art electronic systems by decomposing them into smaller blocks or cells, introducing different levels of abstraction and staged design flows. However, throughout each independently optimised design step, overheads and inefficiencies can accumulate in the resulting overall design. Performing design‐specific optimisation from a more global viewpoint requires more time due to the larger search space but has the potential to provide solutions with improved performanc. In this work, a fully‐automated, multi‐objective (MO) EDA flow is introduced to address this issue. It specifically tunes drive strength mapping, prior to physical implementation, through MO population‐based search algorithms. Designs are evaluated with respect to their power, performance and area (PPA). The proposed approach is aimed at digital circuit optimisation at the block level, where it is capable of expanding the design space and offers a set of trade‐off solutions for different case‐specific utilisation. We have applied the proposed multi‐objective electronic design automation flow (MOEDA) framework to ISCAS‐85 and EPFL benchmark circuits by using a commercial 65 nm standard cell library. The experimental results demonstrate how the MOEDA flow enhances the solutions initially generated by the standard digital flow and how simultaneously a significant improvement in PPA metrics is achieved

Hierarchical Strategies for Efficient Fault Recovery on the Reconfigurable PAnDA Device

A novel hierarchical fault-tolerance methodology for reconfigurable devices is presented. A bespoke multi-reconfigurable FPGA architecture, the programmable analogue and digital array (PAnDA), is introduced allowing fine-grained reconfiguration beyond any other FPGA architecture currently in existence. Fault blind circuit repair strategies, which require no specific information of the nature or location of faults, are developed, exploiting architectural features of PAnDA. Two fault recovery techniques, stochastic and deterministic strategies, are proposed and results of each, as well as a comparison of the two, are presented. Both approaches are based on creating algorithms performing fine-grained hierarchical partial reconfiguration on faulty circuits in order to repair them. While the stochastic approach provides insights into feasibility of the method, the deterministic approach aims to generate optimal repair strategies for generic faults induced into a specific circuit. It is shown that both techniques successfully repair the benchmark circuits used after random faults are induced in random circuit locations, and the deterministic strategies are shown to operate efficiently and effectively after optimisation for a specific use case. The methods are shown to be generally applicable to any circuit on PAnDA, and to be straightforwardly customisable for any FPGA fabric providing some regularity and symmetry in its structure

High-Q Tuneable 10-GHz Bragg Resonator for Oscillator Applications

This paper describes the design, simulation, and measurement of a tuneable 9.365-GHz aperiodic Bragg resonator. The resonator utilizes an aperiodic arrangement of non (λ/4) low-loss alumina plates (εr = 9.75, loss tangent of 1×10−5 to 2 × 10−5) mounted in a cylindrical metal waveguide. Tuning is achieved by varying the length of the center section of the cavity. A multi-element bellows/probe assembly is presented. A tuning range of 130 MHz (1.39%) is demonstrated. The insertion loss S21 varies from −2.84 to −12.03 dB while the unloaded Q varies from 43 788 to 122 550 over this tuning range. At 10 of the 13 measurement points, the unloaded Q exceeds 100 000, and the insertion loss is above −7 dB. Two modeling techniques are discussed; these include a simple ABCD circuit model for rapid simulation and optimization and a 2.5-D field solver, which is used to plot the field distribution inside the cavity

Enclosure shielding assessment using surrogate contents fabricated from radio absorbing material

The electromagnetic environment inside an equipment enclosure at high frequencies is strongly dependent on the absorption of energy by the contents. This effect is neglected by current shielding measurement standards. Here we extended the concept of shielding measurements using surrogate “representative contents” proposed at lower frequencies into the regime were the enclosure is electrically large. We demonstrate how a surrogate fabricated from radio absorbing material can be made to give the same overall absorption as a real printed circuit board and hence produce the same internal environment inside an enclosure during a shielding measurement

Absorption cross section measurement of stacked PCBs in a reverberation chamber

The Absorption Cross Section (ACS) of Printed Circuit Boards (PCBs) can be used to help determine how PCBs affect the internal electromagnetic (EM) field in a shielded enclosure and thus the enclosure shielding effectiveness. Stacked PCBs inside densely populated enclosures may not have the same ACS as the sum of the individual PCBs due to ‘shadowing’ effects. In this paper ACS measurement results from stacked PCBs are presented. The results show that stacking the PCBs close together reduces the ACS and this effect is increased with a greater number of PCBs